https://xidianedu.cc/tech/soc/ 2026-11-05 https://xidianedu.cc/tech/soc/docs-site/ 2026-11-05 https://xidianedu.cc/tech/soc/00-Overview/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/01-soc-fundamentals/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/02-block-diagram/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/03-address-map/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/04-clock-reset-power/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/05-system-flows/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/06-generic-soc-case-study/ 2026-11-05 https://xidianedu.cc/tech/soc/01-SoC-Architecture/07-review-debug-self-test/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/01-isa-pipeline/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/02-privilege-exception/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/03-smp-memory-order/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/04-cases-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/06-exception-vector-context/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/07-atomic-cache-tlb/ 2026-11-05 https://xidianedu.cc/tech/soc/02-CPU-Architecture/08-processor-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/01-cache-organization/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/02-write-coherency/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/03-sram-dram-ddr/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/04-performance-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/06-mesi-moesi/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/07-ddr-timing-interleave/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/08-false-sharing/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/09-memory-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/03-Cache-Memory-Hierarchy/10-icache-dcache-deep-dive/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/01-address-page-table/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/02-tlb-attributes/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/03-mpu-iommu/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/04-mapping-fault/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/06-arm64-page-table-attributes/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/07-smmu-ats-pasid/ 2026-11-05 https://xidianedu.cc/tech/soc/04-MMU-Address-Space/08-address-translation-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/01-amba-axi/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/02-noc-qos-ordering/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/03-bridge-error-performance/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/04-cases-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/06-axi4-waveform-ordering/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/07-noc-routing-credit/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/08-cdc-async-fifo/ 2026-11-05 https://xidianedu.cc/tech/soc/05-Bus-Interconnect/09-interconnect-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/01-dma-descriptor/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/02-coherency-ownership/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/03-barrier-api-iommu/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/04-cases-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/06-linux-dma-api/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/07-ring-scatter-gather/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/08-coherent-interconnect/ 2026-11-05 https://xidianedu.cc/tech/soc/06-DMA-Cache-Coherency/09-dma-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/01-interrupt-controller/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/02-timer-clock/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/03-reset-power-dvfs/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/04-cases-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/06-gic-its-msi/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/07-linux-clock-power/ 2026-11-05 https://xidianedu.cc/tech/soc/07-Interrupt-Clock-Power/08-interrupt-power-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/01-gpio-uart-spi-i2c/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/02-storage/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/03-high-speed/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/04-bringup-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/06-pcie-usb-serdes/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/07-storage-comparison/ 2026-11-05 https://xidianedu.cc/tech/soc/08-Peripherals-High-Speed-IO/08-io-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/01-boot-chain/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/02-ddr-uboot-memory/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/03-dt-bsp-driver/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/04-os-debug/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/06-boot-flow-parameters/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/07-dts-platform-driver/ 2026-11-05 https://xidianedu.cc/tech/soc/09-Boot-BSP-OS/08-boot-bsp-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/01-debug-trace/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/02-crash-register/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/03-performance/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/04-tools-cases/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/05-engineering-analysis/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/06-coresight-jtag/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/07-crash-workflow/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/08-linux-performance-tools/ 2026-11-05 https://xidianedu.cc/tech/soc/10-Debug-Performance/09-debug-performance-engineering-guide/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/01-models-topology/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/02-shared-memory-mailbox/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/03-ipi-doorbell-interrupt/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/04-ring-lockfree-memory-order/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/05-remoteproc-rpmsg-openamp/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/06-lifecycle-recovery/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/07-debug-performance-cases/ 2026-11-05 https://xidianedu.cc/tech/soc/11-Inter-Core-Communication/08-engineering-checklist/ 2026-11-05 https://xidianedu.cc/tech/soc/Case-Studies/ 2026-11-05 https://xidianedu.cc/tech/soc/Case-Studies/01-network-packet-rx-flow/ 2026-11-05 https://xidianedu.cc/tech/soc/Case-Studies/02-cold-boot-to-linux-shell/ 2026-11-05 https://xidianedu.cc/tech/soc/Case-Studies/03-pcie-nvme-read-write/ 2026-11-05 https://xidianedu.cc/tech/soc/Cross-Topics/ 2026-11-05 https://xidianedu.cc/tech/soc/Cross-Topics/01-soc-security-trustzone-pmp/ 2026-11-05 https://xidianedu.cc/tech/soc/Cross-Topics/02-virtualization-smmu-stage2/ 2026-11-05 https://xidianedu.cc/tech/soc/Cross-Topics/03-memory-consistency-models/ 2026-11-05 https://xidianedu.cc/tech/soc/Cross-Topics/04-functional-safety-ras/ 2026-11-05 https://xidianedu.cc/tech/soc/Glossary/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/lab01-qemu-arm64-baremetal-boot/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/lab02-dma-cache-coherency/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/lab03-memory-barrier-litmus/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/lab04-device-tree-driver/ 2026-11-05 https://xidianedu.cc/tech/soc/Labs/lab05-inter-core-ring-doorbell/ 2026-11-05